Alliance Memory Low-Power DDR2 SDRAM are high-speed CMOS and dynamic-access memory that are internally configured as a 8-bank memory device. These DDR2 SDRAM feature 4-bit pre-fetch DDR architecture, programmable READ and WRITE latencies, auto Temperature Compensated Self Refresh (TCSR), and clock stop capability. The DDR2 SDRAM reduces the number of input pins in the system by using a double data rate architecture on the Command/Address (CA) bus. This CA bus is used to transmit address, command, and bank information. These DDR2 SDRAM can achieve high-speed operation by using a double data rate architecture on the DQ (bidirectional/differential data bus) pins.
Features
400MHz maximum clock frequency range4-bit pre-fetch DDR architectureLow voltage power supplyAuto TCSRPartial Array Self Refresh (PASR) power-saving modeDeep Power Down (DPD) modeDriver Strength (DS) controlEight internal banks for concurrent operationMultiplexed, double data rate, and command/address inputs
