Alliance Memory MT41x DDR3 SDRAMs use double data rate architecture with an interface to transfer two data words per clock cycle at I/O pins. The MT41x DDR3's double data rate architecture is an 8n-prefetch architecture that helps to achieve high-speed operations. These SDRAMs operate from CK and CK# differential clock inputs. The MT41x DDR3 employs a burst-orientated approach to read and write with access starting at the selected location and continuing in a programmed sequence. These SDRAMs use READ and WRITE BL8 and BC4. The MT41x DDR3 SRAMs are able to carry out concurrent operations due to their pipelined and multibank architecture. This helps in providing high bandwidth by hiding row precharge and activation time. These SDRAMs feature self-refresh mode, power-saving mode, and power-down mode.
Features
Differential bidirectional data strobe8n-bit prefetch architectureCK and CK# differential clock inputs8 internal banksNominal and dynamic On-Die Termination (ODT) for data, strobe, and mask signalsProgrammable CAS (READ) Latency (CL)Programmable posted CAS Additive Latency (AL)Programmable CAS (WRITE) Latency (CWL)
